1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation regions for FinFET semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width under the channel and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. Such STI structures are typically the very first structures that are formed when manufacturing semiconductor devices. Additionally, very large field isolation regions are formed on a substrate to isolate relative large areas of the substrate.
In general, the formation of a FinFET device involves forming a plurality of trenches in the substrate and eventually filling a portion of those trenches with insulating material. The insulating material within the trenches is generally referred to as local isolation regions for the FinFET device. As device dimensions have decreased, additional problems with the formation of FinFET devices have arisen, particularly as it relates to the formation of local isolation regions, device isolation regions and field isolation regions for FinFET devices. For example, as the width of the fins get smaller, e.g., less than about 30 nm, and as trench width also becomes smaller, it is very difficult to reliably fill such trenches with the local isolation material. Additionally, to the extent a relatively high temperature deposition process is performed to form a liner on the fins after they are formed, the fins may exhibit some undesirable “bending” from their desired perpendicular orientation relative to the surface of the substrate. Such bending tends to make it even more difficult to reliably fill the trenches that define the fins with a void-free insulating material, as “pinch-off” problems are more likely with the smaller-sized trenches.
Efforts to resolve some of the problems above have resulted in device designers implementing several process flows in attempts to solve such problems. However, some of the prior art techniques that have been employed in an attempt to rectify such problems have caused other problems. FIGS. 1A-1E depict several illustrative prior art techniques that have been employed in manufacturing various isolation regions on FinFET devices.
FIG. 1A depicts a prior art FinFET device at the point in fabrication wherein a plurality of fin-forming trenches 12 and a trench 12A for a field isolation region have been formed in a semiconducting substrate 10. The fin-forming trenches 12 define a plurality of fins 14. The size and number of the fins 14 and the trenches 12, 12A may vary.
FIG. 1B depicts one prior art technique wherein multiple layers of spin-on-glass material 16A-16D were formed in the trenches 12, 12A. Typically, a conformably deposited liner layer (not shown) comprised of silicon dioxide was formed in the trenches 12, 12A prior to the formation of the spin-on-glass material 16A-16D. The number of layers of spin-on-glass material depicted in FIG. 1B is by way of example only. Unfortunately, due to the relatively high shrinkage of the spin-on-glass material, defects or cracks 18 were generated in the substrate 10 proximate the relatively larger trench 12A for a field isolation region. Such cracks were typically not observed in the substrate 10 proximate the relatively smaller trenches 12.
FIG. 1C depicts another prior art technique wherein a layer of spin-on-glass material 16 was formed in the trenches 12, 12A, followed by the formation of a CVD-formed oxide material 20. As with the previously described process, a conformably deposited liner layer (not shown) comprised of silicon dioxide was formed in the trenches 12, 12A prior to the formation of the spin-on-glass material 16. Again, due to the relatively high shrinkage of the spin-on-glass material 16, defects or cracks 18 were generated in the substrate 10 proximate the relatively larger trench 12A for a field isolation region. Such cracks were typically not observed in the substrate 10 proximate the relatively smaller trenches 12 that were formed to define the fins 14.
FIGS. 1D-1E depict yet another prior art technique for forming isolation regions for a FinFET device. Initially, a first masking-etching process sequence was performed to form only the fin-forming trenches 12 in the substrate 10 Thereafter, as with the previously described processes, a conformably deposited liner layer (not shown) comprised of silicon dioxide was formed in the trenches 12. Then, as shown in FIG. 1D, a layer of spin-on-glass material 16 was formed in the trenches 12. A capping oxide layer 17 was then formed above the fin region of the substrate 10. Thereafter, as shown in FIG. 1E, a second masking-etching process sequence was performed to form the larger trench 12A. As with the previously described processes, a conformably deposited liner layer (not shown) comprised of silicon dioxide was formed in the trench 12A. Then, a CVD-formed oxide material 20 was formed in the relatively large trench 12A. While this prior art process flow eliminated the cracking problem adjacent the larger trench 12A, it is a much more complex and time-consuming process, requiring at least an additional masking-etching process sequence.
The present disclosure is directed to various methods of forming isolation regions for FinFET semiconductor devices that may solve or reduce one or more of the problems identified above.